1. Field of the Invention
The present invention relates to a semiconductor device and to a manufacturing method for a semiconductor device.
2. Description of Related Art
Increased performance of semiconductor devices in recent years has resulted in practical semiconductor devices operating at high frequencies exceeding the gigahertz level. This improved performance is mostly due to greater miniaturization of circuit elements mainly achieved by tinier gate lengths and suppressing short channel effects to reach higher operating frequencies. In semiconductor devices using signals in the high frequency bands at the gigahertz level or higher, inductor elements must often be highly integrated onto the semiconductor substrate to achieve a broad bandwidth and boost the gain of amplifiers that utilize impedance matching and resonance phenomenon.
Inductor elements function as electronic components by accumulating the magnetic energy in the vicinity of the inductor element. When inductor elements are mounted overlying a semiconductor substrate, eddy current loss due to magnetic fields penetrating to the semiconductor substrate positioned below the inductor element, and wiring near the inductor element cause poor inductor element performance.
Inductor elements used in wireless circuits must have a high Q value (resistance to oscillation i.e. low resistance) in order to achieve low-noise characteristics needed in wireless applications, so a shielded conductor containing slits is formed overlying the semiconductor substrate at a position below the inductor element in order to reduce losses caused by the semiconductor substrate (Japanese Patent Application Publication Nos. 2004-031922 and 2002-093916, and C. P. Yue et al. “On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's”, IEEE Journal of Solid-State Circuits, 1998, Vol. 33, No. 5, 743). There is even magnetic field leakage from the upper section of the inductor element, and inductor elements for radio use utilize wiring with thick film formed in the uppermost layer in order to boost the Q value. Generally, no wiring is formed in the section above the inductor elements so depending on the structure, the problem of magnetic field leakage in the section above the inductor elements can be avoided in communication circuits.
On the other hand, along with the higher operating frequencies in semiconductor devices, increasingly large numbers of inductor elements are being used in logic circuits in recent years. The inductor elements used in logic circuits are typically called, “Peaking inductors.” These peaking inductors are mainly used as amplifier loads and so differ from inductor elements utilized in wireless circuits because a comparatively low Q value is allowed. These peaking inductors on the other hand are mounted in large numbers within the chip and so the inductor elements must occupy a minimal surface area. To ensure that inductor elements take up minimal surface area, technology was proposed for inductor elements having a multilayer structure using wires positioned in the lower layers (International Patent Application No. WO2008/016089).
One method in the related art for lowering magnetic flux leakage to the upper section of the inductor element when a semiconductor device containing an inductor element is mounted over a printed circuit board is shown in FIG. 20. Here, an electromagnetic shielded conductor is formed above the inductor element using a pad wiring layer overlying the inductor element in order to block out mutual interaction from occurring between the inductor element and the wiring in the mounting board (Japanese Patent Application Publication No. 2008-218566).
Moreover, technology was disclosed in Japanese Patent Application Publication No. 2002-198490 for reducing degradation in inductor element characteristics due to the electromagnetic shielded conductor as shown in FIG. 21, by forming an electromagnetic shielded conductor in the lower section and the upper section of the inductor element and then forming an opening in the magnetic flux pass region generated in the center section of the inductor element in the electromagnetic shielded conductor.
International Patent Application No. WO2004/112138, Japanese Patent Application Publication No. 2008-091631, and Japanese Patent Application Publication No. Hei11(1999)-220030 disclose a technology utilizing magnetic material as the electromagnetic shielded conductor.